This invention relates to automated logic circuit design system applicable to the design of large-scale integrated circuits (LSZ's) including microprocessors.
Top-down techniques have been used in the field of LSI design. Such a top-down technique makes a decision about detailed functions required by an LSI, generates a combination of circuit elements of first type (virtual elements) including a logic gate, a register and the like to accomplish such required functions, and transforms the generated virtual elements into circuit elements of second type (real elements) having the same functions as the corresponding virtual elements. The virtual elements are circuit elements each carrying only a functional definition, whereas the real elements, too, are circuit elements but are different from the virtual elements in that transistor configurations for implementation onto a semiconductor chip are already defined. The real elements comply with various target technologies including CMOS and TTL technologies.
The technique mentioned above has been incorporated into many different computer-aided logic design systems. Take one of these logic design systems, for example. Upon being supplied with a functional description expressed by means of high-level programming languages such as C and Prolog, this logic design system first generates configuration data of a first logic circuit (virtual logic circuit) composed of virtual elements and then outputs configuration data of a second logic circuit (real logic circuit) composed of real elements. In another logic design system, a functional description expressed in a flow chart format, which describes desired logic operations, is fed as an input. Circuit configuration data, output from the systems, takes those forms such as a real logic circuit diagram and an element connection information list. At the time when virtual elements are transformed into real elements, a standard cell library storing various information on many real elements such as information about fan-out and delay, is referred to.
In conventional logic design systems, consideration is given to fan-out restrictions and delay constraints when transforming a virtual logic circuit into a real logic circuit. To satisfy such delay constraints, conventionally, the number of real-element stages has been adjusted. No careful considerations, however, have been given to the driving capacity of real elements. This introduces a problem that the circuit transformation is done without much taking care of the characteristics of various technologies. That is, even though an optimal virtual logic circuit is obtained, this may not automatically lead to the fact that an optimal real logic circuit is realized. In addition to this problem, there is another problem that it is not possible to take full advantage of a wealth of information stored in the library.